==============================================================
Guild: wafer.space Community
Channel: 📐 - Designing / 📦-cob / Hey all,
After: 2026-05-31 11:59 p.m.
Before: 2026-07-01 12:00 a.m.
==============================================================

[2026-06-14 9:23 p.m.] rebelmike



[2026-06-14 9:23 p.m.] rebelmike
Cool!  When you say a bunch of bad boards you mean the mezzanine soldering?  It looks like some of the wire bonding isn't perfect either - so it might be a case of sorting through boards to find some that look like all wires are bonded and all pins connected?


[2026-06-15 3:18 a.m.] anfroholic
Yeah, the mezzanine soldering mostly. 
There still may be some issues with a few bonds here or there, but overall we think they are doing much better at improving their processes. 

Is there something in these pictures about the bonds that would make you say that?


[2026-06-15 7:05 a.m.] rebelmike
On the first picture there’s a broken wire on the top left of R1C1, the second diagonal pad has no wire to it. Good to hear that is likely unusual 🙂


[2026-06-15 7:11 a.m.] anfroholic
Ah yeah, good catch. 
A little behind the scenes, they kinda jumped in the middle here and may have taken them for testing before they 'completed' 
The machine does it's part and then they manually inspect them and do some rework if needed on the manual bonder *which is pictured here*.

{Attachments}
2026-06_media/AP1GczPTh2DJ9-wkTAbkUZFDGYJ3FnIQfHUKeEBlDO-B719C.png

{Reactions}
💜

[2026-06-27 2:06 p.m.] rtimothyedwards_19428
Can somebody confirm that the orientation of the simplified diagram of the chip in the https://github.com/wafer-space/ws-run1-cob continuity test results is in fact upside down with respect to the layout?  I used the template padframe and substituted my own dual voltage domain pads, and I kept the power and ground pads in the same locations (or at least I thought I did).  But the pads marked "ground" in the diagram don't match my padframe unless I rotate it 180 degrees.

{Embed}
https://github.com/wafer-space/ws-run1-cob
GitHub - wafer-space/ws-run1-cob: Results from the wafer.space Run ...
Results from the wafer.space Run #1 chip on board packaging. - wafer-space/ws-run1-cob
2026-06_media/ws-run1-cob-4D4DF


[2026-06-27 3:24 p.m.] rebelmike
I would guess this is because the chip is mounted on the CoB rotated. But I can’t confirm for sure


[2026-06-27 5:47 p.m.] anfroholic
Not sure which one you're referring to. This one? Does this help?

{Attachments}
2026-06_media/552fcce82f458a9c6afc87141bbcf59d-9062C.png


[2026-06-28 12:16 a.m.] rtimothyedwards_19428
@Andrew Wingate :  Thanks, that confirms it.  The Wafer Space ship is de-orbiting in the lower left corner, so it has been rotated 180 degrees.  That means I have at least two good boards---One with no continuity errors, and another with one continuity error on an unused pin.  I haven't yet checked the other low-error count boards, since I was waiting on confirmation of orientation.


==============================================================
Exported 9 message(s)
==============================================================